1. Field of the Invention
The present invention relates in general to a semiconductor DRAM (Dynamic Random Access Memory) process. In particular, the present invention relates to a method for forming a bottle-shaped trench.
2. Description of the Related Art
DRAM capacitors generally consist of two electrodes isolated by an insulating material. The electrical charge capability of DRAM is determined by the thickness of the insulating material, the surface area of electrodes and the electrical properties of the insulating material. As ICs become more compact, semiconductor design has reduced device dimensions increasing density to accommodate a large number of memory cells. Conversely, memory cell electrodes must provide sufficient surface area for electrical charge storage.
Under the conditions mentioned above, DRAM trench storage node capacitance is reduced accordingly. Hence, a means of increasing storage capacitance to maintain excellent performance is necessary.
Currently, the preferred method of increasing DRAM storage capacitance is to increase the bottom width of the trench, forming a bottle-shaped capacitor to increase the usable surface area of the trench. Referring to FIGS. 1A˜1F, a semiconductor substrate with a trench is first provided, as shown in FIG. 1A, wherein symbol 100 represents the semiconductor substrate, symbol 102 represents the oxide layer, symbol 104 represents the nitride layer, and symbol 106 represents the trench.
Then, in FIG. 1B, a TEOS (Tetra-Ethyl-Ortho-Silicate) layer is formed conformally as a barrier layer 108. Next, in FIG. 1C, a sacrificial layer 110 comprising polysilicon material, is filled in the bottom of the trench. Next, the barrier layer 108 is removed from the nitride layer 104 and the trench sidewalls not covered by sacrificial layer 110. In FIG. 1D, an oxide layer 112′ is formed conformally on the surface of the nitride layer 104, the trench sidewalls and the sacrificial layer 110.
Subsequently, in FIG. 1E, the oxide layer 112′ covering the nitride layer 104 and the trench bottom is removed by an anisotropic etching to form a collar oxide 112 on the upper sidewalls of the trench, and sacrificial layer 110 is then removed.
Finally, the barrier layer 108 covering the trench bottom is removed using DHF (dilute Hydrofluoric Acid), while the trench sidewalls and semiconductor substrate surface are etched with an NH4OH+H2O etching solution forming the bottle-shaped trench, as shown in FIG. 1F.
When viewed in cross-section, the bottle-shaped trench tapers gradually from the top to the bottom of the trench, presenting a bottle shape. Additionally, a collar oxide can be optionally formed on the upper sidewalls of the trench, as shown in FIG. 2E, or be omitted, as shown in FIG. 3E.
In FIG. 1F, when the trench is etched with NH4OH+H2O etching solution, due to the structure of semiconductor silicon crystal, awl-shaped structures, represented by symbol A, are easily formed at the bottom of the bottle-shaped trench. When this occurs, subsequent formation of the capacitor dielectric layer covering the sidewalls and trench bottom is hindered by poor uniformity of reaction gas (AsH3) diffusion, regardless of whether formation is achieved by gas phase deposition or ASG doping and also results in current leakage.